1. Field of the Invention
The present invention relates to interconnect pads on semiconductor integrated circuits.
2. Description of the Prior Art
In the prior art multiple layered interconnect pads have been used or more specifically, one or more metallic layers disposed on a semiconductor layer have been used in order to obtain electrical contact to an adjoining semiconductor substrate or other regions. The prior art employed a metallic layer to provide a contact surface compatible with subsequent layers, or wire leads, to make external electrical connection. In the prior art this metallic layer has included one or more metallic elements in one layer or one or more metallic layers. Also small amounts of semiconductor material have been deposited with one or more layers of metal to allow saturation of the metal by the semiconductor material, for example, to prevent "spiking" through an underlying diffused region (see U.S. Pat. No. 3,740,835).
None of the prior art interconnect pads which include metallic layers in combination with semiconductor layers have been addressed to the problem of degradation to exposed metal during the lifetime of the device. More particularly, degradation of interconnect pads may occur during the lifetime of the device by the action of two corrosive agents. The first corrosive source includes degrading agents contained within the semiconductor integrated circuit itself. In the case where a contact is positioned directly on passivating layer of the semiconductor integrated circuit, impurities within the passivating layer may combine with water vapor from the environment to form corrosive agents which degrade the electrical performance of the interconnect pad. This may occur even with sealed devices because of imperfections in the seal. For example, phosphorus oxide, contained within a passivating glass layer may act as a deliquescent agent with the ambient water vapor to form phosphoric acid at the interface of the metallic pad and the glass layer. This acid corrodes the metallic pad resulting in electrical and mechanical degradation. A second source (or sources) of corrosive agents are those which are exterior to the semiconductor device. Water vapor, acidic vapors, oxygen and other oxidizing agents may attack the upper exposed surfaces of the metallic pad in an unsealed device or in an imperfectly sealed device. Such agents may destroy the electrical performance of the interconnect pad.
The present invention provides a semiconductor barrier between the metallic pad and the underlying passivating layers such that penetration of extrinsic or intrinsic corrosive agents are excluded from the lower surfaces of the metallic pad. Moreover, the present invention provides a second conductive path whereby electrical coupling between the exterior leads and the semiconductor substrate is preserved even though portions of the metallic interconnect pad may be degraded.